A novel high-performance low-cost double-upset tolerant latch design

HIGHLIGHTS

• who: Jianwei Jiang et al. from the State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and University of Chinese Academy of Sciences, Beijing, China have published the paper: A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design, in the Journal: Electronics 2018, 7, 247 of /2018/
• what: The authors propose a novel high-performance low-cost double-upset (HLDUT) Simulation waveforms have validated the double-upset tolerance of the proposed Besides detailed comparisons demonstrate that the saves 805.24% delay-power-area product (DPAP) on average compared with other . . .
  

   

  

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