A cascade fractional-n synthesizer topology of dll and frequency multiplier for 5g+ communication systems

HIGHLIGHTS

  • What: The aims of the lower-frequency synthesizer are to provide the best in-band phase noise (PN) and the finest channel resolution performances. While report an integrated rms jitter from 10 kHz to 30 MHz, the other references including this work have measured an integrated rms jitter from 1 kHz to 100 MHz. In this article, a new DLL-based synthesizer topology is introduced.
  • Who: Kyu-Hyun Nam et al. from the Department of Electrical Engineering, Kookmin University, Seoul, Republic of Korea have published the paper: A Cascade Fractional-N Synthesizer Topology of DLL . . .

     

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