Reducing avalanche build-up time by integrating a single-photon avalanche diode with a bicmos gating circuit

HIGHLIGHTS

• What: It is shown that the avalanche build-up time of the SPAD integrated in a 0.35 µm (Bi)CMOS technology is almost half that compared to the results reported in [16].
• Who: Bernhard Goll and collaborators from the Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien, Gusshausstrasse, have published the article: Reducing Avalanche Build-Up Time by Integrating a Single-Photon Avalanche Diode with a BiCMOS Gating Circuit, in the Journal: Sensors 2024, 24, 7598. of /2024/
• How: The authors chose 375 fF from this post-layout simulation with additional . . .
  

   

  

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