Shared cache based on content addressable memory in a multi-core architecture

HIGHLIGHTS

  • who: Tech Science Press and colleagues from the Computer Systems Engineering, Arab American University, Jenin, Palestine have published the Article: Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture, in the Journal: (JOURNAL)
  • what: This paper documents the implementation of a Dual-Port Content Addressable Memory (DPCAM) and a modified Near-Far Access Replacement Algorithm (NFRA) which was previously proposed as a shared L2 cache layer in a multi-core processor. The aim of the DPCAM and NFRA design is to allow simultaneous access and achieve less access latency to the shared . . .

     

    Logo ScioWire Beta black

    If you want to have access to all the content you need to log in!

    Thanks :)

    If you don't have an account, you can create one here.

     

Scroll to Top

Add A Knowledge Base Question !

+ = Verify Human or Spambot ?