HIGHLIGHTS
- who: User from the Design Verification, Xilinx, Hyderabad, India Division of Engineering, State University of New York, New Paltz, USA have published the research work: American Journal of Engineering and Applied Sciences, in the Journal: (JOURNAL)
- what: The authors present an energy efficient multiplier design based on effective capacitance minimization.
SUMMARY
Generally, power reduction techniques aim at minimizing all the above mentioned power dissipation sources, but the emphasis here is on dynamic power dissipation as it dominates other power dissipation sources in digital CMOS circuits. But the main focus is the . . .
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