Benchmark figure of merit extensions for low jitter phase locked loops inspired by new pll architectures

HIGHLIGHTS

• who: PLL Architectures et al. from the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA , USA have published the research: Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures, in the Journal: (JOURNAL)
• what: As discussed in the section I and II, one of the main motivations of this work is to include many practical cases where fc is constrained by fref

SUMMARY

???? 2 1? ? ??? ) (1?? )), where σrms and PPLL are the RMS jitter and power consumption of . . .

 



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