Design of a low-power and low-area 8-bit flash adc using a double-tail comparator on 180 nm cmos process

HIGHLIGHTS

• who: Hong-Hai Thai et al. from the Faculty of Electronics and Telecommunications, The University of Science, Vietnam National University, Tokyo, Japan have published the paper: Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process, in the Journal: Sensors 2022, 22, x FOR PEER REVIEW 4.2. of /2022/
• what: After researching various types of comparator architecture, it was decided thatthis thispaper paper would follow thecomparator comparator structure presented . general view this paper would follow the the comparator structure presented.
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