Effects of jfet region design and gate oxide thickness on the static and dynamic performance of 650 v sic planarpower mosfets

HIGHLIGHTS

• who: Shengnan Zhu and collaborators from the Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, USA have published the research work: Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC PlanarPower MOSFETs, in the Journal: Materials 2022, 15, 5995. of /2022/
• what: All the DUTs in this work have similar doping concentration of the epilayer. In this paper, 650 V SiC MOSFETs were designed, fabricated, packaged, and characterized.

SUMMARY

Of 650 V SiC Planar Power MOSFETs. As . . .

 



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