HIGHLIGHTS
- who: IJECE from the Department of Electronics and Communication, College ofDepartment of Electronics and Communication, College of, Andhra Pradesh, India have published the Article: International Journal of Electrical and Computer Engineering (IJECE), in the Journal: (JOURNAL) of Apr/11,/2022
- what: In this paper, a new and delay-efficient structure is proposed for the 4:3 counter using two-bit reordering circuit.
- how: This paper proposes a new and delay-efficient structure for 43 counter using two-bit reordering circuit.
SUMMARY
The delay-efficient 8 and 16-bit multipliers . . .
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