Latency-sensitive high-level synthesis for multiple word-length dsp design

HIGHLIGHTS

• who: Multiple Word-Length DSP Design et al. from the Laboratory UMR-CNRS, Polytechnic Institute of Bordeaux (IPB), University of Bordeaux, Talence , France have published the paper: Latency-Sensitive High-Level Synthesis for Multiple Word-Length DSP Design, in the Journal: (JOURNAL) of 28/06/2010
• what: In this paper an HLS process that takes care of the delay of the operators according to the data width is presented. The methodology the authors propose manages both area- and time-constrained syntheses. The authors address such design approaches, and the authors focus on multiple word-length . . .
  

   

  

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