Novel low voltage and low power array multiplier design for iot applications

HIGHLIGHTS

• who: Jin-Fa Lin et al. from the Department of information and communication, Chaoyang University of Technology, Taichung, Taiwan have published the research: Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications, in the Journal: (JOURNAL)
• what: In this paper a novel latch-adder based multiplier design targeting low voltage and low power IoT applications is presented.

SUMMARY

A key factor in low power multiplier design is the elimination of spurious signal transitions. Complementary enable signals "E" and "E_bar" control the timing of adder outputs. 2.5u/0 . . .

 



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