Perimeter degree technique for the reduction of routing congestion during placement in physical design of vlsi circuits

HIGHLIGHTS

• who: Kuruva Lakshmanna et al. from the Department of Information Technology, Vellore Institute of Technology, Vellore, India have published the research work: Perimeter Degree Technique for the Reduction of Routing Congestion during Placement in Physical Design of VLSI Circuits, in the Journal: Complexity of 27/04/2022
• what: In this study, the ways of robotized floor arranging are investigated, which is critical for the achievement of effective plan space research to be successful. The aim of this work is to identify regions of high dense and recursive routing in chip areas in both horizontal and . . .
  

   

  

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