Verification methods for complex-functional blocks in cad for chips deep submicron design standards

HIGHLIGHTS

• who: Zolnikov Vladimir and collaborators from the Moscow Aviation Institute (National Research University), Volokolamskoe shosse, Moscow, Russia have published the research: Verification methods for complex-functional blocks in CAD for chips deep submicron design standards, in the Journal: (JOURNAL)
• what: The Article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. These features include: integration - the main focus in the verification of SoC is to check the interconnection between the individual blocks of the system. In general, this approach provides a . . .
  

   

  

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