HIGHLIGHTS
- who: Upset-Tolerant D-Latch et al. from the of Electronics and Computer Technology, University of Granada, Granada, Spain have published the article: Highly Reliable Quadruple-Node Upset-Tolerant D-Latch, in the Journal: (JOURNAL)
- what: Scaling CMOS technology increases the demand for D-latch reliability to tackle harsh radiative environments.
SUMMARY
The maximum standard deviations of gate delay of the proposed D-latch, TPDICE-based D-latch, LSEDUT D-latch, DICE, and QNUTL-CG D-latch are 0.0147, 0.016, 0.017, 0.483, and 0.0156, respectively. The . . .
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